1. Field of the Invention
The present invention relates to digital-to-analog converters providing two complementary outputs, and more specifically, to a digital-to-analog converter of R-2R type.
2. Discussion of the Related Art
FIG. 1 schematically shows a conventional digital-to-analog converter of R-2R type. In this type of converter, currents I/2, I/4, I/8 . . . stepped according to a geometric series of ratio 1/2 are generated. The series of currents includes as many currents as there are bits in a digital datum D to be converted (4 in the example of FIG. 1). Each of these currents is directed by a respective switch K to one or the other of two complementary outputs Io, Io* according to a respective bit of datum D. The currents of the series are provided by a network of resistors 10 of R-2R type. A current source 12 draws a current I of network 10 to a low supply potential Vee.
The first current I/2 of the series is provided by a resistor of value 2R connected to current source 12. The second current I/4 of the series is provided by two resistors of values R and 2R connected in series to current source 12. Each of the following currents of the series is provided by two resistors of values R and 2R connected in series to the connection node of the two resistors providing the preceding current.
The last current of the series is provided by a single resistor 13 of value 2R. This last resistor 13 provides a current equal to the penultimate current of the series (I/8 in the example), and must thus be divided by 2 to effectively provide the last current I/16 of the series. In the example shown in FIG. 1, resistor 13 is connected to the emitters of both cascode transistors Q1 and Q1' of identical characteristics, in which the current I/8 provided by resistor 13 is distributed. The bases of transistors Q1 and Q1' are biased by a same voltage Vb1. The last current I/16 of the series is taken from the collector of transistor Q1 while the collector of transistor Q1' is connected to a high supply potential Vcc. To ensure that network 10 and current source 12 operate in proper conditions, switches K are connected to the corresponding resistors of network 10 via respective cascode transistors Q2, the last transistor Q2 being connected between network 10 and cascode transistors Q1 and Q1'. The bases of transistors Q2 are biased by a same voltage Vb2, the collectors are connected to the respective switches K, and the emitters are connected to the corresponding resistors of network 10. The emitter surface areas of transistors Q2 are preferably chosen to be proportional to the currents flowing in these transistors.
With such a converter, each of outputs Io and Io* can take 2.sup.n discrete values, corresponding to the possible combinations of the n bits of datum D. In the example, n=4 and the amplitude of the steps is I/16. Outputs Io and Io* vary in inverse directions with respect to each other.
In some applications, it is desired to generate an analog bipolar signal, that is, a signal which varies between a positive and a negative value, based on digital datum D. This is, for example, the case for a circuit the offset voltage of an amplifier.
By means of a converter of the type of FIG. 1, a bipolar current can be generated. Such a current is obtained by forming the difference Io-Io* of the complementary output currents of the converter.
As shown as an example in FIG. 1, current Io-Io* can be obtained by means of a current mirror 14, the input of which receives current Io. The complementary current Io* is taken from the output of current mirror 14 and the residual current on this output forms the desired current Io-Io*.
Current mirror 14 includes, for example, two PNP transistors Q3 and Q4, the emitters of which are connected to high supply potential Vcc, and the bases of which are interconnected. The collector of transistor Q3 is connected to the base of transistors Q3 and Q4 and receives current Io. The collector of transistor Q4 receives current Io* and supplies current Io-Io*.
FIG. 2 illustrates the variation of signal Io-Io* according to the successive values of datum D. In the example of FIG. 1, datum D varies from 0 to 15. Current Io-Io* varies from -15I/16 to +15I/16 by steps of 2I/16. For example, when datum D is equal to 6 (decimal) or 0110 (binary), the switches K associated with currents I/2 and I/16 are positioned towards output Io*, while the remaining switches K are positioned towards output Io. Thus, current Io* is I/2+I/16=9I/16, while current Io is I/4+I/8=6I/16, whereby current Io-Io* is equal to -3I/16.
There appears to be no value of D for which current Io-Io* is zero. This is a disadvantage in some applications. For example, if such a converter is used to perform an offset setting, a zero offset cannot be obtained.